C8051F310使用功能手册.pdf

SILICON LABSC8051F310/1/2/3/4/5/6/78/16 kB ISP Fl ash MCU Famil yAnal og Peripheral s-10-Bit ADC(C8051F310/1/2/3/6 onl y)Up t o 200 ksps Upt o 21,17,o r 13 ext er nal sing l e-ended o r dif f er ent ial input s VREF f r o m ext er nal pin o r VDD Buil t-in t emper at ur e senso r Ext er nal c o nver sio n st ar t input-Comparat ors Pr o g r ammabl e hyst er esis and r espo nse t ime Co nf ig ur abl e as int er r upt o r r eset so ur c e(Co mpar at o r O)Lo w c ur r ent(L6o.L6Fl ash Memo r y-L2 00 O-k.2 00 O.L2 g-L2 00 O-L2 00 O-L2 g-L2 00 O-L2 00 OL2 g-L2 g2 00O.k2 g-L2 00 O-k.2 00 ORAMCal ibr at ed Int er nal 24.5 MHz Osc il l at o rSMBus/l 2CEnhanc ed SPIUARTTimer s(16-bit)Pr o g r ammabl e Co unt er Ar r ayr ono2 52 52 92 92 52 52 92 92 52 52 92 9Dig it al Po r t I/Osii10-bit 200 ksps ADCiiTemper at ur e Senso r22222222222222Anal o g Co mpar at o r siLead-f r ee(Ro HS Co mpl iant)QFN-24QFN-24QFN-28QFN-28LQFP-32LQFP-32QFN-28QFN-28LQFP-32LQFP-32QFN-28QFN-28LQFP-32LQFP-32Pac kag e18C8051F310/172/3/4/5/6/7Anal o g/Dig it al0/VREF0/C如2/XTAL1 3/XTAL2 4/TX 5/RX 6/CNVSTFigure 1.1.C8051F310 Bl ock DiagramRev.1.719SILICON LABSC8051F310/172/3/4/5/6/7Anal o g/Dig it al Po werDebug HWXTALl Syst em Cl o c kXTAL2-Ext er nal Osc il l at o r Cir c uit2%Int er nal Osc il l at o rPORBr o wn-OutReset8 0 5 1 core16kbyt e FLASH256 byt e SRAM1Kbyt e SRAMSFR Bus0/VREF2/XTAL1 3/XTAL2 4/TX 5/RX6/CNVSTFigure 1.2.C8051F311 Bl ock Diagram20Rev.1.7SILICON LABSC8051F310/172/3/4/5/6/7Anal o g/Dig it al Po werPo r t 3 Lat c h/AIN0-AIN203O/VREF 1 2/XTAL1 3/XTAL2 4/TX 5/RX 6/CNVST0/C2DVDD Figure 1.3.C8051F312 Bl ock DiagramRev.1.721SILICON LABSC8051F310/172/3/4/5/6/7VDD Anal o g/Dig it al Po werGND/RST/C2CKPo r t 3 Lat c h0/VREF12/XTAL13/XTAL24/TX5/RX6/CNVSTFigure 1.4.C8051F313 Bl ock Diagram22Rev.1.7SILICON LABSC8051F310/172/3/4/5/6/70/VREF0/C2D2/XTAL1 3/XTAL2 4/TX 5/RX6/CNVSTFigure 1.5.C8051F314 Bl ock Diagram23SILICON LABSC8051F310/172/3/4/5/6/7Anal o g/Dig it al Pc war8kB FLASH256 byt e SRAM1K byt e SRAMDebug HWXTALl-Syst em Cl o c kXTAL2-*-Int er nal Osc il l at o rPORBr o wn-Outt xt er na Osc il l at o r Cir c uit805C oSFR BusPo r t 3 Lat c h0/VREF 12/XTAL1 3/XTAL2 4/TX 5/RX6/CNVSTP3.0/C2DFigure 1.6.C8051F315 Bl ock Diagram24Rev.1.7SILICON LABSC8051F310/172/3/4/5/6/7VDDGNDAnal o g/Dig it al Po werDebug HW/RST/C2CKXTAL1-Syst em Gl o c kXTAL2 Cl o c k Det ec t o r(o ne-sho t)Int er nal Osc il l at o rExt er nal Osc il l at o r Dr iveSyst em Cl o c kCl o c k Sel ec tPo wer On ResetIqjqeu 山 1CJMCIP-51 Microcont rol l er CoreSyst em Reset(wir ed-OR)ResetFunnel(So f t war e Reset)Er r ant FLASH Oper at io n02qEU 山Ext ended Int er r upt Handl erFigure 1.10.On-Chip Cl ock and Reset28Rev.1.7SILICON LABSC8051F310/172/3/4/5/6/71.2.On-Chip MemoryThe CIP-51 has a st andar d 8051 pr o g r am and dat a addr ess c o nf ig ur at io n.It inc l udes 256 byt es o f dat a RAM,wit h t he upper 128 byt es dual-mapped.Indir ec t addr essing ac c esses t he upper 128 byt es o f g ener al pur po se RAM,and dir ec t addr essing ac c esses t he 128 byt e SFR addr ess spac e.The l o wer 128 byt es o f RAM ar e ac c essibl e via dir ec t and indir ec t addr essing.The f ir st 32 byt es ar e addr essabl e as f o ur banks o f g ener al pur po se r eg ist er s,and t he next 16 byt es c an be byt e addr essabl e o r bit addr essabl e.Pr o g r am memo r y c o nsist s o f 8 o r 16 kB o f Fl ash.This memo r y may be r epr o g r ammed in-syst em in 512 byt e sec t o r s,and r eq uir es no spec ial o f f-c hip pr o g r amming vo l t ag e.See Fig ur e 1.11 f o r t he MCU syst em memo r y map.PROGRAM/DATA MEMORY(Fl ash)DATA MEMORY(RAM)INTERNAL DATA ADDRESS SPACEOxFF0 x80 0 x7F0 x30 0 x2F0 x20 0 x1 F0 x00Upper 128 RAM(Indir ec t Addr essing Onl y)(Dir ec t and Indir ec t Addr essing)Bit Addr essabl eGener al Pur po se Reg ist er sSpec ial Func t io n Reg ist er s(Dir ec t Addr essing Onl y)Lo wer 128 RAM(Dir ec t and Indir ec t/Addr essing)EXTERNAL DATA ADDRESS SPACEOxFFFF0 x04000 x03FF0 x0000Same 1024 byt es as f r o m 0 x0000 t o 0 x03FF,wr apped o n 1 kB bo undar iesXRAM-1024 Byt es(ac c essabl e usin g MOVX ins t r uc t io n)Figure 1.11.On-Board Memory MapRev.1.729SILICON LABSC8051F310/172/3/4/5/6/71.3.On-Chip Debug Circuit ryThe C8051F31x devic es inc l ude o n-c hip Sil ic o n Labs 2-Wir e(C2)debug c ir c uit r y t hat pr o vides no n-int r u-sive,f ul l speed,in-c ir c uit debug g ing o f t he pr o duc t io n par t installed in the end application.Sil ic o n Labs debug g ing syst em suppo r t s inspec t io n and mo dif ic at io n o f memo r y and r eg ist er s,br eakpo int s,and sing l e st epping.No addit io nal t ar g et RAM,pr o g r am memo r y,t imer s,o r c o mmunic at io ns c hannel s ar e r eq uir ed.Al l t he dig it al and anal o g per ipher al s ar e f unc t io nal and wo r k c o r r ec t l y whil e debug g ing.Al l t he per ipher al s(exc ept f o r t he ADC and SMBus)ar e st al l ed when t he MCU is hal t ed,dur ing sing l e st epping,o r at a br eakpo int in o r der t o keep t hem sync hr o nized.The C8051F31ODK devel o pment kit pr o vides al l t he har dwar e and so f t war e nec essar y t o devel o p appl ic at io n c o de and per f o r m in-c ir c uit debug g ing wit h t he C8051F31x MCUs.The kit inc l udes so f t war e wit h a devel o per s st udio and debug g er,an int eg r at ed 8051 assembl er,a debug adapt er,a t ar g et appl ic at io n bo ar d wit h t he asso c iat ed MCU inst al l ed,and t he r eq uir ed c abl es and wal l-mo unt po wer suppl y.The Sil ic o n Labs IDE int er f ac e is a vast l y super io r devel o ping and debug g ing c o nf ig ur at io n,c o mpar ed t o st andar d MCU emul at o r s t hat use o n-bo ar d ICE Chips and r eq uir e t he MCU in t he appl ic at io n bo ar d t o be so c ket ed.Sil ic o n Labs debug par adig m inc r eases ease o f use and pr eser ves t he per f o r manc e o f t he pr ec isio n anal o g per ipher al s.30Devel o pment Envir o nmentSil ic o n Labo r at o r ies Int eg r at edFigure 1.12.Devel opment/l n-Syst em Debug DiagramRev.1.7SILICON LABSC8051F310/172/3/4/5/6/71.4.Programmabl e Digit al I/O and CrossbarC8051F310/2/4 devic es inc l ude 29 I/O pins(t hr ee byt e-wide Po r t s and o ne 5-bit-wide Po r t);C8051F311/3/5 devic es inc l ude 25 I/O pins(t hr ee byt e-wide Po r t s and o ne 1-bit-wide Po r t);C8051F316/7 devic es inc l ude 21 I/O pins(o ne byt e-wide Po r t,t wo 6-bit-wide Po r t s and o ne 1-bit-wide Po r t).The C8051F31x Po r t s behave l ike t ypic al 8051 Po r t s wit h a f ew enhanc ement s.Eac h Po r t pin may be c o nf igur ed as an anal o g input o r a dig it al I/O pin.Pins sel ec t ed as dig it al I/Os may addit io nal l y be c o nf ig ur ed f o r push-pul l o r o pen-dr ain o ut put.The weak pul l ups t hat ar e f ixed o n t ypic al 8051 devic es may be g l o bal l y disabl ed,pr o viding po wer saving s c apabil it ies.The Dig it al Cr o ssbar al l o ws mapping o f int er nal dig it al syst em r eso ur c es t o Po r t I/O pins(See Fig ur e 1.13).On-c hip c o unt er/t imer s,ser ial buses,HW int er r upt s,c o mpar at o r o ut put,and o t her dig it al sig nal s in t he c o nt r o l l er c an be c o nf ig ur ed t o appear o n t he Po r t I/O pins spec if ied in t he Cr o ssbar Co nt r o l r eg ist er s.This al l o ws t he user t o sel ec t t he exac t mix o f g ener al pur po se Po r t I/O and dig it al r eso ur c es needed f o r t he par t ic ul ar appl ic at io n.Hig hest Pr io r it yUARTSPIw-eub-sCBl-bQ(Bu3UDSMBusCPO Out put sCP1 Out put s SYSCLKtod)P2XBR0,XBR1,PnSKIP Reg ist er sPnMDOUT,PnMDIN Reg ist er sPO I/O Cel l spi I/O Cel l sPriorit y DecoderDigit al Crossbar(POOPo G)o-piG)(P2.0-P23)No t es:1.P3.1-P3.4 o nl y avail abl e o n t he C8051F310/2/4.2.P1.6,P1.7,P2.6,P2.7 o nl y avail abl e o n t he C8051F310/1/2/3/4/5一 5P3(P3.0-P34)Figure 1.13.Digit al Crossbar DiagramRev.1.7P2 I/O Cel l sP3 I/O Cel l s31SILICON LABSC8051F310/172/3/4/5/6/71.5.Serial Port sThe C8051 F31x Famil y inc l udes an SMBus/l 2C int er f ac e,a f ul l-dupl ex UART wit h enhanc ed baud r at e c o nf ig ur at io n,and an Enhanc ed SPI int er f ac e.Eac h o f t he ser ial buses is f ul l y impl ement ed in har dwar e and makes ext ensive use o f t he CIP-51s int er r upt s,t hus r eq uir ing ver y l it t l e CPU int er vent io n.1.6.Programmabl e Count er ArrayAn o n-c hip Pr o g r ammabl e Co unt er/Timer Ar r ay(PCA)is inc l uded in addit io n t o t he f o ur 16-bit g ener al purpo se c o unt er/t imer s.The PCA c o nsist s o f a dedic at ed 16-bit c o unt er/t imer t ime base wit h f ive pr o g r ammabl e c apt ur e/c o mpar e mo dul es.The PCA c l o c k is der ived f r o m o ne o f six so ur c es:t he syst em c l o c k divided by 12,t he syst em c l o c k divided by 4,Timer 0 o ver f l o ws,an Ext er nal Cl o c k Input(ECI),t he syst em c l o c k,o r t he ext er nal o sc il l at o r c l o c k so ur c e divided by 8.The ext er nal c l o c k so ur c e sel ec t io n is usef ul f o r r eal-t ime c l o c k f unc t io nal it y,wher e t he PCA is c l o c ked by an ext er nal so ur c e whil e t he int er nal o sc il l at o r dr ives t he syst em c l o c k.Eac h c apt ur e/c o mpar e mo dul e c an be c o nf ig ur ed t o o per at e in o ne o f six mo des:Edg e-Tr ig g er ed Capt ur e,So f t war e Timer,Hig h Speed Out put,8-o r 16-bit Pul se Widt h Mo dul at o r,o r Fr eq uenc y Out put.Addit io nal l y,Capt ur e/Co mpar e Mo dul e 4 o f f er s wat c hdo g t imer(WDT)c apabil it ies.Fo l l o wing a syst em r eset,Mo dul e 4 is c o nf ig ur ed and enabl ed in WDT mo de.The PCA Capt ur e/Co mpar e Mo dul e I/O and Ext er nal Cl o c k Input may be r o ut ed t o Po r t I/O via t he Dig it al Cr o ssbar.32Cr o ssbarFigure 1.14.PCA Bl ock DiagramRev.1.7SILICON LABSC8051F310/172/3/4/5/6/71.7.10-Bit Anal og t o Digit al Convert erThe C8051F310/1/2/3/6 devic es inc l ude an o n-c hip 10-bit SAR ADC wit h a 25-c hannel dif f er ent ial input mul t ipl exer.Wit h a maximum t hr o ug hput o f 200 ksps,t he ADC o f f er s t r ue 10-bit ac c ur ac y wit h an INL o f 1LSB.The ADC syst em inc l udes a c o nf ig ur abl e anal o g mul t ipl exer t hat sel ec t s bo t h po sit ive and neg at ive ADC input s.Po r t s 1-3 ar e avail abl e as an ADC input s;addit io nal l y,t he o n-c hip Temper at ur e Senso r o ut put and t he po wer suppl y vo l t ag e(VDD)ar e avail abl e as ADC input s.User f ir mwar e may shut do wn t he ADC t o save po wer.Co nver sio ns c an be st ar t ed in six ways:a so f t war e c o mmand,an o ver f l o w o f Timer 0,1,2,o r 3,o r an ext er nal c o nver t st ar t sig nal.This f l exibil it y al l o ws t he st ar t o f c o nver sio n t o be t r ig g er ed by so f t war e event s,a per io dic sig nal(t imer o ver f l o ws),o r ext er nal HW sig nal s.Co nver sio n c o mpl et io ns ar e indic at ed by a st at us bit and an int er r upt(if enabl ed).The r esul t ing 10-bit dat a wo r d is l at c hed int o t he ADC dat a SFRs upo n c o mpl et io n o f a c o nver sio n.Windo w c o mpar e r eg ist er s f o r t he ADC dat a c an be c o nf ig ur ed t o int er r upt t he c o nt r o l l er when ADC dat a is eit her wit hin o r o ut side o f a spec if ied r ang e.The ADC c an mo nit o r a key vo l t ag e c o nt inuo usl y in bac kg r o und mo de,but no t int er r upt t he c o nt r o l l er unl ess t he c o nver t ed dat a is wit hin/o ut side t he spec if ied r ang e.Anal o g Mul t ipl exerPi.6,P1.7available onC8051F310/1/2/3/4/5P2.6,P2.7available onC8051F310/1/2/3/4/5tf芟一一 一 7 0 4 2,3.3.p F pP3.1-3.4 available on C8051F310/2VDDTemp-Senso r sP1.6,P 1.7 available onC8051F310/1/2/3/4/5P2.6,P2.7available on C8051F310/1/2/3/4/5P3.1-3.4 available on C8051F310/2P3.4-oVREFGND000001St ar t Co nver sio nCo nf ig ur at io n,Co nt r o l,and Dat a Reg ist er s10-BltADCEnd o f Co nver sio nInt er r uptWindo w Co mpar e Int er r uptWindo w Co mpar e Lo g icADC Dat a Reg ist er sSARAD0BUSY(W)-Timer 0 Over f l o w-Timer 2 Over f l o w-Timer 1 Over f l o w CNVSTR Input-Timer 3 Over f l o wFigure 1.15.10-Bit ADC Bl ock DiagramRev.1.733SILICON LABSC8051F310/172/3/4/5/6/71.8.Comparat orsC8051 F31x devic es inc l ude t wo o n-c hip vo l t ag e c o mpar at o r s t hat ar e enabl ed/disabl ed and c o nf ig ur ed via user so f t war e.Po r t I/O pins may be c o nf ig ur ed as c o mpar at o r input s via a sel ec t io n mux.Two c o mpar at o r o ut put s may be r o ut ed t o a Po r t pin if desir ed:a l at c hed o ut put and/o r an unl at c hed(async hr o no us)o ut put.Co mpar at o r r espo nse t ime is pr o g r ammabl e,al l o wing t he user t o sel ec t bet ween hig h-speed and l o w-po wer mo des.Po sit ive and neg at ive hyst er esis ar e al so c o nf ig ur abl e.Co mpar at o r int er r upt s may be g ener at ed o n r ising,f al l ing,o r bo t h edg es.When in IDLE mo de,t hese int err upt s may be used as a wake-up so ur c e.Co mpar at o r O may al so be c o nf ig ur ed as a r eset so ur c e.Fig ur e 1.16 sho ws he Co mpar at o r O bl o c k diag r am.CMX0N1CMX0N0CMX0P1CMX0P0CPOEN CPOOUT CPORIF CPOFIFCP0HYP1 CPOHYPQ CP0HYN1 CP0HYN0VDDCPO Int er r uptP1.4P2.0|P2.4P1.0CP0+pl5 n GND(SYNCHRONIZER)CPORising-edg eCPO Fal l ing-edg eL-Lo g ic _ _Cr o ssbarCPOCP0-CPOA31Figure 1.16.Comparat orO Bl ock Diagram34Rev.1.7SILICON LABSC8051F310/172/3/4/5/6/72.Absol ut e Maximum Rat ingsTabl e 2.1.Absol ut e Maximum Rat ings*Paramet erCondit ionsMinTypMaxUnit sAmbient t emper at ur e under bias-55125St o r ag e Temper at ur e-65150Vo l t ag e o n any Po r t I/O Pin o r RST wit h r espec t t o GND-0.35.8VVo l t ag e o n VDD wit h r espec t t o GND-0.34.2VMaximum To t al c ur r ent t hr o ug h VDD and GND500mAMaximum o ut put c ur r ent sunk by RST o r any Po r t pin100mA*Not e:St r esses abo ve t ho se l ist ed under Abso l ut e Maximum Rat ing s may c ause per manent damag e t o t he devic e.This is a st r ess r at ing o nl y and f unc t io nal o per at io n o f t he devic es at t ho se o r any o t her c o ndit io ns abo ve t ho se indic at ed in t he o per at io n l ist ing s o f t his spec if ic at io n is no t impl ied.Expo sur e t o maximum r at ing c o ndit io ns f o r ext ended per io ds may af f ec t devic e r el iabil it y.Rev.1.7SILICON LABSC8051F310/172/3/4/5/6/73.Gl obal DC El ect rical Charact erist ics-40 t o+85,25 MHz Syst em Cl o c k unl ess o t her wise spec if ied.Tabl e 3.1.Gl obal DC El ect rical Charact erist icsParamet erCondit ionsMinTypMaxUnit sDig it al Suppl y Vo l t ag eVRST13.03.6VDig it al Suppl y RAM Dat a Ret ent io n Vo l t ag e1.5VSpec if ied Oper at ing Temper at ur e Rang e-40+85SYSCLK(syst em c l o c k f r eq uenc y)O225MHzTsysl(SYSCLK l o w t ime)18nsTsysh(SYSCLK hig h t ime)18nsDigit al Suppl y CurrentCPU Act ive(Normal Mode,fet ching inst ruct ions from Fl ash)Idd(No t e 3)VDD=3.0 V,F=25 MHzVDD=3.0 V,F=1 MHzVDD=3.0 V,F=80 kHzVDD=3.6 V,F=25 MHz7.80.383110.78.612.1mA mA RA mAlDD Suppl y Sensit ivit y(No t e 3,No t e 4)F=25 MHzF=1 MHz6762%/V%/VlDD Fr eq uenc y Sensit ivit y(No t e 3,No t e 5)VDD=3.0 V,F 15 MHz,T=25 QC VDD=