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1、使用LabVIEW FPGA模块开发可编程自动化控制器学院: 通信与电子工程学院 班级: 电子071 学号: 姓名: Building Programmable Automation Controllers with LabVIEW FPGAOverviewProgrammable Automation Controllers (PACs) are gaining acceptance within the industrial control market as the ideal solution for applications that require highly integrate
2、d analog and digital I/O, floating-point processing, and seamless connectivity to multiple processing nodes. National Instruments offers a variety of PAC solutions powered by one common software development environment, NI LabVIEW. With LabVIEW, you can build custom I/O interfaces for industrial app
3、lications using add-on software, such as the NI LabVIEW FPGA Module. With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instruments delivers an intuitive, accessible solution for incorporating the flexibility and customizability of FPGA technology into industrial PAC system
4、s. You can define the logic embedded in FPGA chips across the family of RIO hardware targets without knowing low-level hardware description languages (HDLs) or board-level hardware design details, as well as quickly define hardware for ultrahigh-speed control, customized timing and synchronization,
5、low-level signal processing, and custom I/O with analog, digital, and counters within a single device. You also can integrate your custom NI RIO hardware with image acquisition and analysis, motion control, and industrial protocols, such as CAN and RS232, to rapidly prototype and implement a complet
6、e PAC system.Table of Contents1. Introduction 2. NI RIO Hardware for PACs 3. Building PACs with LabVIEW and the LabVIEW FPGA Module 4. FPGA Development Flow 5. Using NI SoftMotion to Create Custom Motion Controllers 6. Applications 7. Conclusion Introduction You can use graphical programming in LabV
7、IEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices. RIO technology, the merging of LabVIEW graphical programming with FPGAs on NI RIO hardware, provides a flexible platform for creating sophisticated measurement and control systems that you could
8、previously create only with custom-designed hardware.An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can configure and reconfigure the logic on FPGAs for your specific appl
9、ication. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. The flexible, software-programmable architecture of FPGAs offer benefits such as high-performance execution of cus
10、tom algorithms, precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. While FPGAs are often u
11、sed in industrial control products, FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complex design tools used more by hardware design engineers than by control engineers.Withinthet
12、est-fixturethetxoutputofthetransmittermoduleisloopedbacktotherxinputofthereceivermodule.Thisallowsthetransmittermoduletobeusedastestsignalgeneratorforthereceivermodule.Datacanbewritteninparallelformattothetransmittermoduleandloopedbackinserialformattotherxinputofthereceivermodule,anddatareceivedcanf
13、inallybereadoutinparallelformatfromthereceivermodule.InordertoautomatethetestingoftheUARTasmuchaspossible,treeindependentVerilogtaskswerewrittenasfollows.TheVerilog task“write_to_transmitter”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatawritesequencetothetransmittermodule.Datathata
14、rewrittentothetransmitteruponexecutionofthe“write_to_transmitter”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“read_out_receiver”holdsallnecessarystatementsrequiredtogenerateasingle paralleldatareadoutsequencefromthereceivermodule.Datathatarereadoutofthereceiveruponexecutio
15、nofthe“read_out_receiver”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“compare_data”holdsallnecessarystatementsrequiredtocomparethepreviousdatawrittentothetransmittermodule,to thecorrespondingandmostrecentdatareceivedandreadoutfromthereceivermodule.Ifanydiscrepancyoccurs,th
16、e“compare_data”taskflagsforanerrorbywritingoutthedatavaluesthatwerewrittentothetransmittermodule,aswellasthecorrespondingdatavaluesthatwerereceivedbyandreadoutfromthereceivermodule.Thesimulationisimmediatelystoppedbythe“compare_data”taskifanydiscrepancyoccurs.BesidesthetreeabovementionedVerilogtasks
17、,thetest-fixtureholdsthestatementstogeneratethemclkx16,themasterresetsignalsaswellasthe“txtorx”loopbackfeature.Thestatementsareconsideredtrivial,andwillnotbeillustratedhere,butcanbereferredtowithinthetest-fixtureitself.Thecoreofthetest-fixtureisabehaviorallevel“forloop”thatexecutesthetreeabovementio
18、nedVerilogtasksinordertowriteallpossibledatacombinationstothetransmitterandverifythatsamedatagetsproperlyreceivedbythereceiver.Theforloopisshowed below in figure 21.Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout(bidirectional),andcanbereferredtointable1.Nexttoth
19、e specificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenuseforseque
20、ntiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsusto describethefunction
21、ofthetransmitterinamorebehavioralmanner,ratherthanfocusonitsactualimplementationatgatelevelInsoftwareprogramminglanguage, functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandtasksasconstructs,analogoustosoftwarefun
22、ctionsandprocedures.AVerilogfunctionand taskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymainta
23、in.AVerilogfunction canhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”modeWith the LabVIEW FPGA Module an
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