NI pxie-582 features功能指南使用手册.pdf

2023-03-01PXIe-5820 FeaturesPXIe-5820 Feat uresCont ent sPXIe-5820.3PXIe-5820.3PXIe-5820 Block Diagram.7FPGA Basecard Subsyst em.8l/Q Input.18l/Q O ut put.19Cable Select ion.20Different ial O perat ion.22Synchronizat ion Using NI-RFSA and NI-RFSG.23Ext ernal Device Int erface Considerat ions.23Device Warm-Up.24Power O n,Reset,and Download Condit ions.24Calibrat ion.25Self-Calibrat ion.26NI-TClk Manual Calibrat ion Using NI-RFSA.29NI-TClk Manual Calibrat ion Using NI-RFSG.30Unsupport ed NI-RFSG Feat ures.31/PXIe-5820 FeaturesPXIe-5820500 MHz,1 GHz l/Q Bandwidt h,Baseband PXI Vect or Signal Transceiver 1 GHz complex l/Q equalized bandwidt h DC t o 500 MHz frequency rangePXIe-5820 National InstrumentsPXIe-5820 FeaturesFigure 1.PXIe-5820 Front Panel and LEDsNlPXIe-S20Vectorgaseband IQ.1.25 GS/sO oQ+。5._，4 PXIe-5820 FeaturesTable 1.General Connect or Descript ionsConnect orDescript ionConnect or TypeREFINInput connect or t hat allows for t he use of an ext ernal 10 MHz Reference Clock.MMPX(f)REF O UTO ut put connect or t hat can export a 10 MHz Reference Clock.MMPX(f)PFIOProgrammable-funct ion digit al I/O(DIO)connect or for use wit h t riggers or event s.MMPX(f)DIOMult i-signal DIO connect or t hat provides access t o FPGA mult i-gigabit t ransceivers(MGTs)and general purpose LVCMO S signals.Nano-Pit ch I/OConnect orDescript ionConnect or Typel/QO UT 1+O ut put connect or for 1+MMPX(f)signals.1-O ut put connect or for 1-signals.MMPX(f)Q+O ut put connect or for Q+signals.MMPX(f)Q-O ut put connect or for Q-signals.MMPX(f)l/QIN 1+Input connect or for 1+signals.MMPX(f)1-Input connect or for 1-signals.MMPX(f)Q+Input connect or for Q+signals.MMPX(f)National InstrumentsPXIe-5820 FeaturesSolid greenThe device is generat ing a waveform.Connect orDescript ionConnect or TypeQ-Input connect or for Q-signals.MMPX(f)Table 2.1/Q Connect or Descript ionsLEDIndicat ionsACCESSIndicat es t he basic hardware st at us of t he device.O ffThe device is not yet funct ional or has det ect ed a problem wit h a PXI Express power rail.AmberThe device is being accessed.Accessed means t hat you are writ ing t o t he device set up regist ers t o cont rol t he device,reading from t he device t o monit or t he device st at us,or t ransferring dat a t o/from t he device.GreenThe device is cont rollable t hrough t he soft ware.ACTIVEO ffThe device is idle.Dim amberThe device is wait ing for an acquisit ion Reference Trigger.Solid amberThe device is acquiring a waveform.Solid redThe device has det ect ed an error.The LED remains red unt il t he error condit ion is removed.Not The indicat ors are list ed in increasing order of priorit y.For example,if you are generat ing a waveform using NI-RFSG and wait ing6 PXIe-5820 FeaturesTable 3.LED Indicat orsLEDIndicat ionson an acquisit ion Reference Trigger in NI-RFSA,t he LED is dim amber.Figure 2.PXIe-5820 DIO Connect or Pinout/ReservedAlBl5.0 VGNDA2B2GNDMGT Rx+0A3B3MGTTx+0MGT Rx-0A4B4MGTTx-0GNDA5B5GNDMGT Rx+1A6B6MGTTx+1MGT Rx-1A7B7MGT Tx-1GNDA8B8GNDDIO 4A9B9DIO 6DIO 5A10BIODIO 7GNDAllBllGNDMGTREF+/DIOOA12B12DIO 2MGT REF-/DIO 1A13B13DIO 3GNDA14B14GNDMGT Rx+2A15B15MGT Tx+2MGT Rx-2A16B16MGT Tx-2GNDA17B17GNDMGT Rx+3A18B18MGT Tx+3MGT Rx-3A19B19MGT Tx-3GNDA20B20GND5.0 VA21B21ReservedPXIe-5820 Block DiagramThe PXIe-5820 has t he l/Q Input,l/Q O ut put,and FPGA Basecard subsyst ems.National InstrumentsPXIe-5820 FeaturesMGT.Ditigal I/ODIOPCIe Gen 3 x8 A DRAM SRAMPXI TriggersFPGA BasecardouCQ-dispm ssaidx 山xd/Not e Some calibrat ion-relat ed rout ing pat hs and front panel connect ors have been omit t ed from t he illust rat ion of t he high-level block diagram for simplicit y.Relat ed concept s:l/Q Input l/Q O ut put FPGA Basecard Subsyst emFPGA Basecard Subsyst emThe PXIe-5820 has an FPGA basecard,represent ed by t he following high-level block diagram.8 PXIe-5820 Features UCO5-0ECDssedx 山-xdThe FPGA basecard of t he PXIe-5820 consist s of t he following component s:FPGA,Clocking,ADCs and DACs,PFI 0,Digit al I/O,DRAM,SRAM,PCIe Int erface,and PXI t riggers.Xilinx Virt ex-7 FPGAThe PXIe-5820 cont ains a Xilinx Virt ex-7 VX690T FPGA,which is used for syst em configurat ion,digit al dat a movement,and digit al signal processing.The FPGA has direct connect ions t o t he ADC,DAC,PCI Express bus,DRAM,SRAM,PFI 0,digit al I/O,and PXI t rigger lines,allowing for cust om programming using LabVIEW FPGA t o meet t he needs of many t ypes of applicat ions.The Xilinx Virt ex-7 FPGA has t he following resources.Table 4.Reconfigurable FPGA ResourcesResource TypeNumberSlice regist ers866,400Slice look-up t ables(LUT)433,200DSP48E1S360018 Kb block RAMs2940Clocking National InstrumentsPXIe-5820 FeaturesThe PXIe-5820 has mult iple clocks available on t he device and inside t he FPGA.The main device clock is t he Sample Clock,which is used t o clock t he ADC,clock t he DAC,and creat e t he Dat a Clock for t he relat ed FPGA logic.Sample ClockThe Sample Clock runs at 1.25 GHz and is export ed by t he phase-locked loop(PLL).You can select one of t he following resources as t he reference signal for t he PLL:The int ernal t emperat ure compensat ed cryst al oscillat or(TCXO)The PXIe-5820REF IN front panel connect or PXI_CLO CKWhile t he Sample Clock frequency is fixed at 1.25 GHz,you can achieve high-resolut ion l/Q dat a rat es using t he Fract ional Int erpolat or and Fract ional Decimat or DSP FPGA Vis.Dat a ClockThe Sample Clock is divided by eight t o creat e t he Dat a Clock,which is sent t o t he FPGA.The Dat a Clock runs at 156.25 MHz,and it is t he main clock used for t he acquisit ion and generat ion dat a pat hs inside t he FPGA.Because t he Dat a Clock is one-eight h t he rat e of t he Sample Clock,eight samples are processed on each cycle of t he Dat a Clock.ADC FPGA DACFPGA ClocksThe following t able list s t he clocks available in t he FPGA.In addit ion t o t hese clocks,LabVIEW FPGA allows for derived clocks at user-defined frequencies.10 PXIe-5820 FeaturesNameFrequency(MHz)Descript ionDat a Clock156.25Main clock used for t he acquisit ion and generat ion dat a pat hs in t he FPGA.Dat a Clock x2312.5In-phase wit h t he Dat a Clock and used for DSP Vis.Dat a Clock x4625In-phase wit h t he Dat a Clock.40 MHz O nboard Clock40Free-running 40 MHz oscillat or.200 MHz O nboard Clock200Free-running 200 MHz oscillat or.PXIe_CLK100100100 MHz clock from t he backplane.Front Panel Clocking Connect orsYou can use t he PXIe-5820 REF IN front panel connect or t o apply an ext ernal 10 MHz reference t o t he device.Relat ed reference:PXIe-5820DRAMThe PXIe-5820 has t wo banks of dynamic random-access memory(DRAM),which are independent ly accessible from t he FPGA.Refer t o t he PXIe-5820 Specifications document for informat ion about t he DRAM size and t hroughput.These DRAM banks are general purpose,but t hey are oft en used for st oring waveforms t o be generat ed or waveforms t hat have been acquired.Not e Nat ional Inst rument s recommends using LabVIEW FPGA memory it ems for most applicat ions requiring t he use of DRAM.Relat ed t asks:Configuring DRAM wit h FPGA Memory It emsConfiguring DRAM wit h FPGA Memory It ems National InstrumentsPXIe-5820 FeaturesUse t he FPGA memory it em int erface t o use DRAM in t he same way t hat you use block memory and look-up t ables(LUT).DRAM memory it ems appear in t he Project Explorer window undert he FPGA t arget.The FPGA memory it em int erface allows you t o part it ion t he physical DRAM banks int o mult iple memory it ems.Complet e t he following st eps t o configure DRAM wit h FPGA memory it ems.1.To creat e a t arget-scoped memory it em,right-click t he FPGA t arget in t he Project Explorer window and select New Memory from t he short cut menu.The Memory Propert ies dialog box appears.2.Select DRAM from t he Implement at ion pull-down menu.3.Select t he DRAM bank you want t o use from t he DRAM bank pull-down menu.4.Type in t he number of element s based upon your desired memory size in t he Request ed number of element s t ext box.5.Click O K in t he Memory Propert ies dialog box.The memory it em is now populat ed in t he Project Explorer window undert he t arget.6.Use t he memory it em in an FPGA VI.SRAMThe PXIe-5820 has one bank of st at ic random-access memory(SRAM),which is accessible from t he FPGA.Refer t o t he PXIe-5820 Specifications document for informat ion about t he SRAM size and t hroughput.SRAM Int erfaceThe PXIe-5820 support s SRAM access t hrough socket ed component-level IP(CLIP).Refer t o t he PXIe-5820 Specifications document t o det ermine t he available amount of onboard SRAM for your device.Relat ed t asks:Configuring SRAM wit h Socket ed CUPConfiguring SRAM wit h Socket ed CLIP上 PXIe-5820 FeaturesUse t he socket ed CLIP int erface t o communicat e direct ly wit h t he onboard SRAM.Socket ed CLIP list s all memory int erfaces t hat are compat ible wit h t he SRAM.The SRAM CLIP is present in t he LabVIEW project by default but is disabled.Complet e t he following st eps t o configure SRAM wit h socket ed CLIP:1.Right-click t he SRAM CLIP and select Propert ies from t he short cut menu t o display t he SRAM Propert ies dialog box.2.Select Enable Memory if it is not already select ed t o display t he SRAM configurat ion opt ions.3.Select t he appropriat e clock for your project in t he Clock Select ions dialog box.You can use t he SRAM CLIP in any single clock domain.You can select only clocks already added t o t he project.Relat ed concept s:SRAM Propert ies Dialog BoxSRAM Propert ies Dialog BoxRight-click t he SRAM Bank it em in t he Project Explorer window and select Propert ies from t he short cut menu t o display t his dialog box.Check t he Enable SRAM checkbox if it is not already select ed t o display t he following pages in t he Cat egory list:General Clock Select ionsGeneral PageUse t he General page t o configure t he t ype of memory int erface t hat should be used when communicat ing wit h ext ernal SRAM.To display t his page,in t he SRAM Propert ies dialog box,select General from t he Cat egory list.This page cont ains t he following component s:Enable SRAM Enables t he SRAM.Unchecking t his box disables access t o t he SRAM.National InstrumentsPXIe-5820 Features Memory Int erfaceList s all memory int erfaces t hat are compat ible wit h t he SRAM.If mult iple versions of a memory int erface are available,t he version informat ion displays next t o t he memory int erface name.Det ailsDisplays general informat ion about t he SRAM memory int erface.Pat hDisplays t he file syst em pat h t o t he XML file for t he current ly select ed memory int erface file.ReloadReloads t he current ly select ed memory int erface in t he t able.Use t he Reload but t on if you modify a memory int erface XML file on disk aft er you configure it for use wit h your FPGA t arget.Reload updat es t he I/O in t he LabVIEW project and det ails informat ion,but changes may not be visible in t he Memory Int erface or Pat h dialog boxes.The PXIe-5820 ships wit h one memory int erface support opt ion,which provides access t o t he ext ernal SRAM memory.Clock Select ions PageUse t he Clock Select ions page t o link each clock port defined by t he componentlevel IP(CLIP)t o a clock on t he FPGA t arget.You must add t he FPGA clock t o t he LabVIEW project before you can link t o t he FPGA clock.To display t his page,in t he SRAM Propert ies dialog box,select Clock Select ions from t he Cat egory list.This page includes t he following component s:Component-Level IP ClockList s clock(s)defined in t he CLIP declarat ion XML file.Connect ionList s clocks available on t he FPGA t arget.Power and Thermal Monit oring and Shut down Condit ionsThe PXIe-5820 is prot ect ed against excessive t emperat ures and power consumpt ion and shut s down in t he presence of excessive heat or power consumpt ion.When t he module shut s down,it aut omat ically loads a low-power,nearly empt y FPGA image.Any user inst rument driver session or FPGA I/O st ops,and any program t hat t ries t o read or writ e t o t he module ret urns an error.To recover from t hermal shut down,resolve t he excessive t emperat ure and rest art t he syst em,or reset t he device from MAX.Check t hat t he ambient t emperat ure 14 PXIe-5820 Featuresaround t he chassis is wit hin specificat ions and t hat t he device is receiving proper airflow.Make sure t hat chassis fans are clean and t hat filler panels or slot blockers cover any empt y slot s t o maximize cooling airflow.Posit ion t he chassis so t hat inlet and out let vent s are not obst ruct ed.To recover from an over-power shut down,rest art t he syst em or reset t he device from MAX.Avoid running t he applicat ion or FPGA VI t hat t riggered t he excess power consumpt ion.Reducing t he ambient t emperat ure and improving cooling and airflow may also reduce power consumpt ion.Monit or t emperat ure and power consumpt ion in your applicat ion t o det ect shut down condit ions.To monit or how far t he module is from t he t emperat ure limit,use t he FPGA Temperat ure propert y or t he NIRFSA_ATTR_FPGA_TEMPERATURE at t ribut e.The t hermal shut down limit is.To monit or how far t he module is from t he power limit,use t he Module Power Consumpt ion propert y or t he NIRFSA_ATTR_MO DULE_PO WER_CO NSUMPTIO N at t ribut e.The power consumpt ion shut down limit is.Not e Ensure your applicat ion has a wide enough margin t o allow for t emperat ure and power variat ions bet ween your development environment and deployment environment.The deployed applicat ion may run hot t er or cooler t han in it does in development due t o hardware differences or variat ions in ambient t emperat ure,airflow,chassis posit ioning,adjacent modules,power consumpt ion,and ot her fact ors.Relat ed informat ion:-NI-RFSA Programming ReferencePCI Express Int erfaceThe PXIe-5820 has a PCI Express(up t o Gen3 x8)backplane connect ion,which is used for programmed I/O,DMA t ransfers,and peer-t o-peer st reaming.DIGITAL I/O(DIO)The PXIe-5820 DIGITAL I/O(DIO)connect or support s eight parallel LVCMO S lines in addit ion t o four lanes of high speed serial mult i-gigabit t ransceivers(MGT),using a 42-pin Molex Nano-Pit ch I/O connect or.The eight LVCMO S lines support 1.2 V,1.5 V,1.8 V,2.5 V,and 3.3 V volt age levels and can be used in a variet y of applicat ions including serial peripheral int erface bus(SPI),int er-int egrat ed circuit(I2C)bus,and National InstrumentsPXIe-5820 Featuresdigit al t riggering and event s.You can cont rol t he lines direct ly from t he inst rument s onboard FPGA.The PXIe-5820 DIGITAL I/O(DIO)can use DIO signals in a variet y of applicat ions including serial peripheral int erface bus(SPI),int er-int egrat ed circuit(l2C)bus,anddigit al t riggering and event s.Signal TypeMGT Tx Xilinx Virt ex-7 GTHDirect ion Descript ionO ut put Dedicat ed MGTt ransmit different ial pairs(AC-coupled).MGT Rx Input Dedicat ed MGT receivedifferent ial pairs(AC-coupled).MGT REF Different ialUser reference clock sourc