《电子技术数字基础-Digital-Fundamentals》双语-第08章-Counters.ppt
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1、Chapter 8 Counters(and the Sequential Logic)1.ContentswIntroductionwAnalysis of the Sequential LogicwCounterswDesign of Sequential Logics2.8-0 IntroductionwThe digital electronic logic is classified as the combinational logic and the sequential logic.w(数字电路分为:数字电路分为:组合逻辑电路及时序逻辑电路组合逻辑电路及时序逻辑电路)wThe s
2、equential logic includes the combinational logic section and the memory section.3.8-0 Introduction The logic diagram for the general sequential logicCom-Com-bina-bina-tional tional LogicLogicMeMemormory yx x x x1 1 1 1x x x xi i i i y y y y1 1 1 1y y y yj j j j q q q q1 1 1 1q q q ql l l l z z z z1
3、1 1 1z z z zk k k k X=X=X=X=(x1,x2,xi,)(x1,x2,xi,)Y=(yY=(yY=(yY=(y1 1 1 1,y,y,y,y2 2 2 2,y,y,y,yj j j j,),),),)Q=Q=Q=Q=(q1,q2,ql,)(q1,q2,ql,)Z=(zZ=(zZ=(zZ=(z1 1 1 1,z,z,z,z2 2 2 2,z,z,z,zk k k k,),),),)Y=FX,QY=FX,QY=FX,QY=FX,QZ=GX,QZ=GX,QZ=GX,QZ=GX,QQ Q Q Qn+1n+1n+1n+1=HZ,Q=HZ,Q=HZ,Q=HZ,Qn n n n Out
4、put Output Output Output Exp.Exp.Exp.Exp.State Exp.State Exp.State Exp.State Exp.Excitation Excitation Excitation Excitation Exp.Exp.Exp.Exp.输出方程驱动方程状态方程4.8-0 IntroductionwThe sequential logic is classified as the asynchronous one and synchronous one(异步时序异步时序电路和同步时序电路)电路和同步时序电路).wThe analysis and de
5、sign of the sequential logic is discussed in this chapter.And the counter is the most useful device.5.8-2 Synchronous Counter Operation(同步计数器)&Analysis of the Sequential Logic(时序电路分析)wSynchronous(同步同步):Events that have a fixed time relationship with each other.wSynchronous counter:the counter whose
6、flip-flop(FF)are clocked at the same time by a common clock pulse.6.8-2-1 Analysis of the Sequential LogicwWhats the function of the following logic diagram?How to analyze this diagram?7.8-2-1 Analysis of the Sequential Logic-ProcedureProcedure:1.Write down the clock and excitation expressions for e
7、ach FF.2.Get their state expressions by replacing the logic expression for the FF with its excitation expression.1.1.写出每个触发器的时钟方程和驱动方程;写出每个触发器的时钟方程和驱动方程;2.2.将驱动方程代入触发器的特性方程,得到状态方程组;将驱动方程代入触发器的特性方程,得到状态方程组;8.8-2-1 Analysis of the Sequential Logic-Procedure3.3.写出输出方程;写出输出方程;5.5.说明电路的逻辑功能。说明电路的逻辑功能。4.4
8、.依次假定依次假定初态初态,计算计算次态次态,画出画出状态转换图状态转换图(表表)或或 时序波形图时序波形图 。3.Write down the output expression;4.Assume the present state,and analyze the next state,and draw its state diagram(状态转换图状态转换图)/state sequence table(状态转换表状态转换表)or its timing diagram(时序图)(时序图).5.Determine the logic function of the logic diagram.
9、9.8-2-1 Analysis of the Sequential Logic Example1wEx.1 Determine the logic function.Synchronous Sequential Logic1.Write down the clock and excitation expressions for each FF.Toggle at the positive edge.T FFJ=K=110.8-2-1 Analysis of the Sequential Logic Example14.Assume the present sate,and analyze t
10、he next state,and draw its state diagram/state sequence table or its timing diagram.11.8-2-1 1 Analysis of the Sequential Logic State Sequence Table(状态转换表)State Sequence Table12.8-2-1 Analysis of the Sequential Logic State Diagram(状态转换图)00000000010101011010101011111111State Sequence TableState Diagr
11、amQ Q Q Q1 1 1 1Q Q Q Q0 0 0 013.8-2-1 Analysis of the Sequential Logic Timing Diagram(时序图)Timing Diagram14.8-2-2 A 2-Bit Synchronous Binary Counter00000000010101011010101011111111A 2-bit synchronous binary counter(2位同步二进制位同步二进制/4进制进制 加法计数器)加法计数器)15.8-2-3 A 3-Bit Synchronous Binary CounterwEx.2 Dete
12、rmine the logic function.16.8-2-3 A 3-Bit Synchronous Binary Counter17.8-2-3 A 3-Bit Synchronous Binary CounterA 3-bit synchronous binary counter(3位同步二进制位同步二进制/8进制进制 加法计数器)加法计数器)18.8-2-4 A 4-Bit Synchronous Decade Counter19.8-2-4 A 4-Bit Synchronous Decade Counter20.8-2-4 A 4-Bit Synchronous Decade
13、CounterA 1-bit synchronous decade counter(同步十进制加法计数器)同步十进制加法计数器)21.8-1 Asynchronous Counter Operation (异步计数器异步计数器)wAsynchronous:refers to events that do not have a fixed time relationship with each other and,generally,do not occur at the same time.wAsynchronous counter:counter in which the FF do not
14、 change states at exactly the same time because they do not have a common clock pulse.22.8-1-1 Analysis of Asynchronous Sequential LogicwDetermine the logic function.Asynchronous Sequential Logic23.8-1-1 Analysis of Asynchronous Sequential Logic24.8-1-1 Analysis of Asynchronous Sequential Logic25.8-
15、1-1 Analysis of Asynchronous Sequential Logic26.8-1-1 Analysis of Asynchronous Sequential Logic27.8-1-1 Analysis of Asynchronous Sequential LogicState Sequence TableState DiagramA asynchronous decade counter(异步十进制加法计数器)异步十进制加法计数器)28.8-1-2 Some Useful ConceptswValid states(used states)(有效状态)states us
16、ed by the diagram in normal operation.wInvalid states(unused states)(无效状态)states which arent used by the diagram in normal operation.29.8-1-2 Some Useful ConceptsValid StatesInvalid StatesValid CycleInvalid Cycle30.8-1-2 Some Useful ConceptswValid Cycle(有效循环)Cycle that includes the valid states.wInv
17、alid Cycle(无效循环)Cycle that includes the invalid states.31.8-1-2 Some Useful ConceptswStartup automatically(自启动功能)If a logic diagram doesnt have invalid cycle(无效循环),it can startup automatically.(电路进入无效状态之后电路进入无效状态之后,在在CPCP脉冲作用下脉冲作用下,能自动返回有能自动返回有效循环效循环,称电路能够自启动称电路能够自启动,否则为不能自启动)否则为不能自启动)wSelf-startup
18、check(自启动检查)Check if all the invalid states can enter the valid cycle automatically.32.State DiagramStartup automaticallySelf-startup check33.8-3 Counters 8-3-1 Categories of CountersThe counter can be classified as the following categories:34.8-3-1 Categories of CountersModulus-2 counter (2进制)进制)Mo
19、dulus-10 counter(10进制)进制)Modulus-60 counter(60进制)进制)Modulus-M counter(M进制进制,任意进制)任意进制)35.8-2-5 Synchronous Binary CountersQn+1=TQn+TQnC=Q0Q1Q2Q3Negative edge-triggered 36.8-2-5 Synchronous Binary Countersf01/2f01/4f01/8f01/16f01/16f0The counter is also called the frequency divider(分频器分频器).C=Q0Q1Q2Q3
20、37.8-2-5 Synchronous Binary Counters-74161 MSI modulus-16 counterCounter,Divider,Modulus-16(16进制进制)38.8-2-5 74161 MSI modulus-16 counterParallel data inputs(并行输入端)并行输入端)Data outputs/States Clock PulseActive at the positive edgeENT,ENP:Enable Pins 39.8-2-5 74161 MSI modulus-16 counter40.8-2-5 74161 M
21、SI modulus-16 counterPreset input(Load)(预置端)预置端)(同步预置同步预置)Active-low,synchronously Clear input(清零端)清零端)(异步清零异步清零)Active-low,asynchronously 41.8-2-5 74161 MSI modulus-16 counterAt the terminal count of 15,RCO=1.Ripple clock output(进位脉冲进位脉冲)42.8-2-5 74161 MSI modulus-16 counterState DiagramTiming Diag
22、ram43.8-2-5 74161/74163 MSI modulus-16 counterLogic Function Table(功能表)功能表)for 74161/7416344.8-2-5 74161/74163 MSI modulus-16 counterClear input(清零端)清零端)(异步清零异步清零)Active-low,asynchronously 45.8-2-5 74161/74163 MSI modulus-16 counterPreset input(Load)(预置端)预置端)(同步预置同步预置)Active-low,synchronously 46.8-2
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